1. Field of the Invention
The present invention relates generally to semiconductor packaging and, more specifically, to lowering the inductance in integrated circuit packages.
2. Description of Related Art
It is generally desirable to have a semiconductor package which is more efficient and has high decoupling capacitance/low inductance. It is known that the effective inductance can be lowered by connecting decoupling capacitors to a circuit. Inductance is a function of path length, therefore the longer the current path, the higher the inductance. High inductance, which yields higher supply noise in semiconductor packages, reduces the performance of integrated circuits(ICs). Also, inductance between an IC and power supply can induce spurious voltage spikes in the power supply system, which can in turn cause timing problems in signal switching.
Decoupling capacitors are housed on semiconductor packages, in order to lower the inductance through the package. Decoupling capacitors shunt power and ground planes or power and ground leads so that rapid voltage changes in the device result in an electrical short circuit across the capacitor, compensating voltage spikes with a stored charge on the decoupling capacitor. The stored charge either dissipates or is used as a local power supply to device inputs during signal switching stages, allowing the decoupling capacitor to negate the effects of voltage noise induced into the system by parasitic inductance.
One way decoupling capacitors have been used in the past is shown in FIG. 1. As shown, a semiconductor package substrate 100 that houses an IC 111 is attached to a printed circuit board 119. The IC 111 is coupled to a semiconductor package substrate 100 by a plurality of solder connections 115, and in turn the semiconductor package substrate 100 is coupled to printed circuit board 119 by a plurality of solder connections 114. A decoupling capacitor 112 is electrically coupled by a plurality of solder connections 116 to power connections 105 and ground connections 106 of an IC 111 through a power plane 120 and a ground plane 121. The current path 113 from the IC 111 to the decoupling capacitor 112 travels through the power plane 120 and ground plane 121 of semiconductor package substrate 100 in the manner illustrated in FIG. 1. Problems arise in this prior art package, because the current path 113 that is parallel to the IC 111, between the IC 111 and the decoupling capacitor 112, is long and creates high inductance. Therefore, it is desirable to reduce the parallel current flow in order to keep inductance at a minimum.
Another problem with the prior art, which leads to higher inductance, is the existence of separate power and ground planes. The separation distance between the planes 120 and 121 contributes to the inductance problem by extending the current path 113 between the IC and the decoupling capacitor. Another problem associated with this arrangement of separate ground and power planes is an increased inductance due to each current flowing through each connection, without a current opposing the same. Although decoupling capacitors are necessary, if a better power supply and return arrangement to and from an IC is obtained, it would be possible to reduce inductance and have higher performance ICs.
Since semiconductor packages are small and have space constraints, capacitors that are placed on a semiconductor package must also be small. Smaller capacitors are costly. In addition, the space constraints associated with present day semiconductor packages make it difficult to rotate capacitors, which is important in order to reduce Electro Magnetic Interference(EMI). EMI is unwanted electronic noise produced by high frequency electronic circuits which can induce malfunctions in electronic equipment. This EMI would effect the performance of other chips and nearby systems.
It would therefore be desirable to provide a semiconductor package which provides for a reduction of the inductance and better power supply delivery to an IC.